Principal Emulation Engineer

productivity through scripting (Python, Perl, Tcl, shell) and tooling enhancements. - Interface with EDA vendors (Synopsys...

Lugar: Santa Clara, CA | 05/05/2026 19:05:37 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Principal Analog Layout Engineer

“Virtuoso VXL†and/or Synopsys “Custom Compiler†layout tools. Experienced in Mentor Graphics “Calibre†drc/lvs verification...

Lugar: San Diego, CA | 16/07/2026 20:07:38 PM | Salario: S/. $152300 - 225440 per year | Empresa: Marvell

FPGA Engineer

Experience with FPGA design, simulation, and verification tools (Synopsys, Riviera, ModelSim, Questasim, etc.) A desire to push...

Lugar: Chicago, IL | 01/05/2026 20:05:45 PM | Salario: S/. $175000 - 225000 per year | Empresa: Belvedere Trading

Senior Analog Layout Manager

. Proficient in Synopsys or CADENCE layout entry tools;programming skills in Skill, Ample, or Perl are a plus. Strong technical...

Lugar: San Diego, CA | 30/04/2026 18:04:49 PM | Salario: S/. $138200 - 204460 per year | Empresa: Marvell

Forward Deployed Engineer

(e.g., Qualcomm SNPE/QNN, NVIDIA TensorRT/Jetson field engineering, Ceva, Cadence Tensilica, Synopsys ARC, Arm, Hailo...

Lugar: Burlingame, CA | 23/07/2026 17:07:47 PM | Salario: S/. $150000 - 200000 per year | Empresa: quadric, Inc

Static Timing Analysis (STA) Engineer

signoff and at least one ASIC tape-out. Good understanding of RTL to GDS flow Proficiency using Synopsys Primetime... (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis Ability to work with large...

Lugar: Tukwila, WA | 22/07/2026 00:07:05 AM | Salario: S/. $146200 - 197800 per year | Empresa: Boeing