HBM SoC RTL Design Engineer

considerations. Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens. Programming or scripting experience (e.g...

Lugar: Folsom, CA | 01/08/2026 22:08:14 PM | Salario: S/. $121000 - 247000 per year | Empresa: Micron

Synthesis-DFT Stitch CAD Engineer

, leveraging both Synopsys and Cadence solutions and tools. Improving the SoC Synthesis and DFT Stitch methodologies for diverse...

Lugar: San Diego, CA | 01/08/2026 02:08:37 AM | Salario: S/. $164000 - 246000 per year | Empresa: Qualcomm

STA Engineer

‑on experience with: Synopsys Prime Time Synopsys Design Compiler / Cadence Genus Preferred Qualifications Implementation...

Lugar: Santa Clara, CA | 01/08/2026 02:08:55 AM | Salario: S/. $153200 - 229800 per year | Empresa: Qualcomm

Principal Analog Layout Engineer

“Virtuoso VXL†and/or Synopsys “Custom Compiler†layout tools. Experienced in Mentor Graphics “Calibre†drc/lvs verification...

Lugar: San Diego, CA | 16/07/2026 19:07:40 PM | Salario: S/. $152300 - 225440 per year | Empresa: Marvell

HBM SoC Physical Design Engineer

. Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent). Solid...

Lugar: Folsom, CA | 02/08/2026 01:08:26 AM | Salario: S/. $121000 - 205000 per year | Empresa: Micron