FPGA Design Verification Engineer
, Synopsys VCS, Haps). · Experience with high-speed I/O design and protocols. Knowledge of PCIe, I2C, SPI, etc. · Hands...
Lugar: Mountain View, CA | 24/01/2026 23:01:53 PM | Salario: S/. $101000 - 152000 per year | Empresa: UST