Senior Digital ASIC Design Engineer Synthesis (m/f/d)

and at scale. Job Duties & Responsibilities Architecture development for CMOS designs Design and RTL coding of digital and full... development cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard...

Lugar: Baden-Württemberg | 14/07/2026 17:07:24 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer (m/f/d)

Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/cases... Circuit (ASIC) design methodologies and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog...

Lugar: Baden-Württemberg | 14/07/2026 17:07:29 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior ASIC Design Engineer DfT (m/f/d)

Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... and BIST Knowledge of digital, mixed signal, RF and power device test methodologies Experience in Register Transfer Level (RTL) coding...

Lugar: Baden-Württemberg | 14/07/2026 17:07:56 PM | Salario: S/. No Especificado | Empresa: Advantest

Expert Digital ASIC Design Engineer (m/f/d)

Design and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/cases... in digital design (SOC), ASIC design methodologies and silicon development cycle Experience in Register Transfer Level (RTL...

Lugar: Baden-Württemberg | 14/07/2026 17:07:38 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Staff Engineer Digital Design (f/m/div)

partitioning Conduct RTL design and implementation of digital logic and integration of clock management analog mixed-signal IPs..., with a focus on automotive, safety-critical systems, and power management systems Proficiency in RTL coding using System Verilog...

Lugar: München, Bayern | 10/07/2026 00:07:56 AM | Salario: S/. No Especificado | Empresa: Infineon