Senior Software Engineer API - Node.js, SQL

– fast, hands-on, and without unnecessary meeting overhead. smartclip is the adtech development unit of RTL Group — Europe... of smartclip will merge with RTL AdConnect and G&J iMS to form RTL AdAlliance, an international advertising and technology sales...

Lugar: Hamburg | 16/04/2026 17:04:23 PM | Salario: S/. No Especificado | Empresa: Smartclip

DSP ASIC Design Engineer - Optical Transmission Systems

architecture and functional requirements to define and refine digital design specifications Develop, integrate, and optimize RTL...‑on expertise with C++ development for High‑Level Synthesis (HLS) Proficiency in generating RTL from C++ models using CatapultC...

Lugar: Braunschweig, Niedersachsen | 13/04/2026 02:04:18 AM | Salario: S/. No Especificado | Empresa: Ciena

Senior Digital ASIC Design Engineer (m/f/d)

and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/cases generation... (ASIC) design methodologies and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog...

Lugar: Deutschland | 08/04/2026 01:04:18 AM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer (m/f/d)

Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs...

Lugar: Deutschland | 07/04/2026 23:04:06 PM | Salario: S/. No Especificado | Empresa: Advantest

Expert Digital ASIC Design Engineer (m/f/d)

& Responsibilities Requirements gathering and elicitation for devices and IP Architecture development for CMOS designs Design and RTL... in digital design (SOC), ASIC design methodologies and silicon development cycle Experience in Register Transfer Level (RTL...

Lugar: Deutschland | 07/04/2026 17:04:40 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer Synthesis (m/f/d)

& Responsibilities Architecture development for CMOS designs Design and RTL coding of digital and full-custom modules Verification... cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation...

Lugar: Deutschland | 07/04/2026 17:04:31 PM | Salario: S/. No Especificado | Empresa: Advantest

Senior Digital ASIC Design Engineer (m/f/d)

Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs...

Lugar: Deutschland | 07/04/2026 17:04:59 PM | Salario: S/. No Especificado | Empresa: Advantest

FPGA Design Engineer (m/f/d)

families and IP for timing‑critical and safety‑related functions. Develop synthesizable RTL (VHDL) for: PWM generators... and a solid understanding of synthesizable RTL design, timing constraints, and clock domain crossing techniques. Hands...

Lugar: Berlin | 04/04/2026 01:04:41 AM | Salario: S/. No Especificado | Empresa: GE Vernova