FPGA Designer (m/f/d) Space

and execution of test benches for RTL and timing simulations Formal verification of FPGA designs, including timing analysis, code...

Lugar: München, Bayern | 18/12/2024 18:12:47 PM | Salario: S/. €60000 - 90000 per year | Empresa: Orizon

Cellular IP Design Engineer (m/f/d)

design and quality checks such as Lint and CDC/RDC. Proficient in using (System)Verilog, the ability to analyze RTL/Netlist... in RTL design, Firmware, System Engineering, Power, and Physical-Design teams. English language proficiency is a requirement...

Lugar: München, Bayern | 28/11/2024 00:11:07 AM | Salario: S/. No Especificado | Empresa: Apple

Working Student Financial Controlling und Billing (w/m/d)

for numbers Independent, structured work approach and team player Fluent in German and good English skills About us At RTL... countries and in the US, we exclusively represent only the best video publishers such as RTL, M6, ITV or Activision Blizzard...

Lugar: Hamburg - Paris | 19/11/2024 23:11:49 PM | Salario: S/. No Especificado

Experienced AMS Digital Design Engineer (m/f/d)

creative RTL Design Engineer. As a part of our multifaceted group, you will have the rare and great opportunity to craft... Verilog RTL according to specification - Partition the function between HW and FW for most efficient implementation - Develop...

Lugar: München, Bayern | 12/11/2024 02:11:41 AM | Salario: S/. No Especificado | Empresa: Apple

Silicon Validation Engineer (m/f/d)

architecture Experience and/or are interested in silicon and RTL test and debug Key Qualifications Key Qualifications...-silicon verification environments (RTL simulation, emulation and FPGA prototyping) is a plus English language fluency...

Lugar: München, Bayern | 24/10/2024 23:10:16 PM | Salario: S/. No Especificado | Empresa: Apple

Cellular SoC Frontend STA Engineer (m/f/d)

as well as design- and timing analysis. Together with RTL designers, Physical designers, and other integration teams..., and revision control systems (e.g. PerForce) Very good experience with Verilog and the ability to analyze RTL/Netlist designs...

Lugar: München, Bayern | 20/10/2024 01:10:40 AM | Salario: S/. No Especificado | Empresa: Apple