– fast, hands-on, and without unnecessary meeting overhead. smartclip is the adtech development unit of RTL Group — Europe... of smartclip will merge with RTL AdConnect and G&J iMS to form RTL AdAlliance, an international advertising and technology sales...
Lugar:
Hamburg | 16/04/2026 17:04:23 PM | Salario: S/. No Especificado | Empresa:
Smartclip, with around 75,000 employees operating in more than 50 countries worldwide. Its portfolio brings together market leaders such as RTL Group, Penguin...
architecture and functional requirements to define and refine digital design specifications Develop, integrate, and optimize RTL...‑on expertise with C++ development for High‑Level Synthesis (HLS) Proficiency in generating RTL from C++ models using CatapultC...
and RTL coding of digital and full-custom modules Verification on module and chip level including test plan/cases generation... (ASIC) design methodologies and silicon development cycle Experience in Register Transfer Level (RTL) coding (Verilog...
Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs...
& Responsibilities Requirements gathering and elicitation for devices and IP Architecture development for CMOS designs Design and RTL... in digital design (SOC), ASIC design methodologies and silicon development cycle Experience in Register Transfer Level (RTL...
& Responsibilities Architecture development for CMOS designs Design and RTL coding of digital and full-custom modules Verification... cycle Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog) Experience with standard simulation...
Architecture development for CMOS IP designs Design and RTL coding of digital and full-custom modules Verification on module... Experience in Register Transfer Level (RTL) coding (Verilog) Experience with standard simulation tools for digital designs...
families and IP for timing‑critical and safety‑related functions. Develop synthesizable RTL (VHDL) for: PWM generators... and a solid understanding of synthesizable RTL design, timing constraints, and clock domain crossing techniques. Hands...
Lugar:
Berlin | 04/04/2026 01:04:41 AM | Salario: S/. No Especificado | Empresa:
GE Vernova Bertelsmann, whose other content businesses include the entertainment company RTL Group and the trade book publisher Penguin...