Principal Physical Design Engineer
all blocks, IPs, and sub-chips at a large SoC level. Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad... level. Experience in custom place and route. Exposure to 2.5D/3D packaging is preferred. High performance and large...
Lugar: Sunnyvale, CA | 13/03/2026 02:03:24 AM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise