DFM Valor Engineer

Qualifications: Experience with scripting for automation (VBScript, Python). Familiarity with other EDA tools and basic netlist...

Lugar: Irvine, CA - Palo Alto, CA | 05/12/2025 19:12:27 PM | Salario: S/. No Especificado | Empresa: Rivian

Sr. Staff Physical Design Manager

Must have a background in ASIC or SOC development Physical design knowledge, from netlist handoff to GDS tape-out including floor planning... record of team mentorship for high performance Technical leadership of ASIC or SOC Netlist to GDS tape-out Experience...

Lugar: Morrisville, NC | 27/11/2025 23:11:44 PM | Salario: S/. $158900 - 235210 per year | Empresa: Marvell

Senior Staff Physical Design Manager

in lieu of a formal degree Must have a background in ASIC or SOC development Physical design knowledge, from netlist... of ASIC or SOC Netlist to GDS tape-out Experience as either top-level physical design lead, STA chip Lead or chip DFT lead...

Lugar: Santa Clara, CA | 21/11/2025 00:11:34 AM | Salario: S/. $157170 - 235400 per year | Empresa: Marvell

Senior CPU Power Architect

. What you’ll be doing: Pre-silicon Power Estimation: Model and estimate CPU power at C-model, RTL, and netlist stages using.... Strong understanding of leakage and dynamic power in VLSI circuits Experience with RTL and netlist power analysis tools such as Power...

Lugar: Santa Clara, CA | 19/11/2025 21:11:54 PM | Salario: S/. No Especificado | Empresa: Nvidia

CAD and PPA Methodology Engineer

tools · Design constraint management for power, timing, clocking, interfaces · Formal Verification for RTL-netlist... and netlist-netlist checks · Clock Tree Analysis and Optimization · ECO methods for functional and timing fixes · Managing...

Lugar: San Diego, CA | 18/11/2025 23:11:19 PM | Salario: S/. No Especificado | Empresa: Qualcomm