tools Design constraint management for power, timing, clocking, interfaces Formal Verification for RTL-netlist and netlist...-netlist checks Clock Tree Analysis and Optimization At-least 5-7 years of experience developing methodologies for PPA...
and design patterns Experience in the areas of RTL Synthesis (System Verilog ->Netlist), Clock Tree Optimization, Exposure...
. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist. Support...
and sequences. Maintain scripts for netlist release and programming instruction generation. Diagnose failed tests and manage bug...
requirements. Experience in Logical Equivalence Checking (LEC) (RTL-to-Netlist and Netlist-to-Netlist). Understanding of SOC...
issues. Optimize design for power, performance, and area (PPA). Conduct formal equivalence checks between RTL and netlist...
with front end design teams to address timing, power and congestion challenges Deliver a synthesized netlist to ASIC BE vendor...
level place and route assignments from Netlist through GDS flow Perform full chip implementation of complex SoCs (RTL...
modelling of analog blocks and DMS netlist generation. Continuous interaction with analog mixed signal and firmware teams... Virtuoso for managing dms_configs, SystemVerilog/wreal views and creating DMS netlist. Proficiency in Scripting languages...
(CI) pipelines to ensure PDK updates do not break legacy designs or connectivity logic. Netlist & Connectivity: Own the logic... for netlist extraction, ensuring that the connectivity graph generated by the code perfectly matches the physical intent...