EDA/CAD Software Engineer, Staff
in the areas of RTL Synthesis (System Verilog ->Netlist), Clock Tree Optimization, Exposure to VLSI design concepts...
Lugar: San Diego, CA | 08/10/2026 18:10:44 PM | Salario: S/. No Especificado | Empresa: Qualcomm
Scientist, Electrical Engineer
from RTL design through structural netlist timing closure including CDC and UPF. 5+ years' experience in schematics design...
Lugar: Yorba Linda, CA | 08/10/2026 17:10:05 PM | Salario: S/. $153000 per year | Empresa: L3Harris Technologies
Memory System Designer and Place and Route Engineer
, LVS, EM/IR, etc. Gate netlist synthesis Skill Set Required Strong design skills Ability to write and debug Verilog...
Chip Lead / Physical Design Director
Design and Design for Test teams, driving complex customer SoC projects from RTL or Netlist to GDS. These critical SoCs...
Lugar: Austin, TX | 07/10/2026 21:10:07 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
ASIC Engineering Technical Leader
, compression/decompression logic, memory BIST, and logic BIST, using Siemens Tessent tools for RTL and gate netlist DFT...
Lugar: Sunnyvale, CA | 07/10/2026 17:10:31 PM | Salario: S/. $55 per hour | Empresa: Omega Solutions Inc
ASIC DFT Engineer
you will own DFT insertion, verification, DRC check, and test coverage closure from RTL/netlist through post-silicon debug...
Lugar: Palo Alto, CA | 07/10/2026 02:10:37 AM | Salario: S/. No Especificado | Empresa: Rivian
ASIC Physical Design Engineer — Synthesis and Timing – (Associate or Experienced)
, timing and power convergence, and ECO implementation Ensure clean netlist handoffs and predictable convergence...
Lugar: El Segundo, CA - Los Angeles, CA | 06/10/2026 01:10:48 AM | Salario: S/. $98600 - 133400 per year | Empresa: Boeing
Sr DFT/ATPG Engineer–Mixed-Signal IP
;identify and resolve simulation failures, timing issues, X-propagation, and model or netlist mismatches. Own the generation..., netlist, constraint, clocking, reset, timing, and X-propagation issues. Knowledge of zero-delay and SDF-annotated simulation...
Lugar: Fort Collins, CO | 03/10/2026 17:10:50 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices
Principal SoC DFT Engineer
from RTL/netlist through post-silicon debug. As a senior member of the DFT team, you will work closely with the architecture... Experience developing and validating scan and test-mode timing constraints End-to-end DFT lifecycle experience, from RTL/netlist...
Lugar: San Jose, CA | 03/10/2026 17:10:24 PM | Salario: S/. No Especificado | Empresa: Nokia
Principal Design Engineer
(GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior. Sign-off: Define the...
Lugar: Austin, TX | 03/10/2026 01:10:20 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems