EDA/CAD SW Engineer

and design patterns Experience in the areas of RTL Synthesis (System Verilog - Netlist), Clock Tree Optimization, Exposure...

Lugar: San Diego, CA | 25/10/2025 19:10:23 PM | Salario: S/. No Especificado | Empresa: Qualcomm

SoC Physical Design Engineer, PnR

partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology. Description - Work.... - Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. - Timing, physical and electrical...

Lugar: Beaverton, OR | 24/10/2025 22:10:22 PM | Salario: S/. No Especificado | Empresa: Apple

FE Design and Timing Engineer

to Post Synthesis netlist. Exposure to industry standard Timing, Logic Equivalence, Physical Design and Synthesis tools...

Lugar: San Diego, CA | 24/10/2025 21:10:05 PM | Salario: S/. No Especificado | Empresa: Apple

FE Design and Timing Engineer

to Post Synthesis netlist. Exposure to industry standard Timing, Logic Equivalence, Physical Design and Synthesis tools...

Lugar: San Diego, CA | 24/10/2025 20:10:29 PM | Salario: S/. No Especificado | Empresa: Apple

Timing Radio Integration Engineer

of ATPG and DFT support for SOC scan debug chains and their timing to the radio sub-cells. Analog modeling & netlist...

Lugar: Irvine, CA | 15/10/2025 18:10:47 PM | Salario: S/. No Especificado | Empresa: Apple
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