Design Engineer

power analysis at various design stages, spanning from RTL to GDSII. Contribute to the development, improvement... processes. Investigate and address power inefficiencies, providing actionable feedback to the RTL design team. Minimum...

Lugar: Austin, TX | 03/04/2026 17:04:39 PM | Salario: S/. $45 - 50 per hour | Empresa: TekWissen

Front End Infrastructure Engineer

used for RTL architecture and ensure they interface cleanly with front-end verification flows. Maintain and refine... digital simulation and verification tools, plus tools used for RTL architectural analysis and configuration. Advanced...

Lugar: San Diego, CA | 19/02/2026 21:02:46 PM | Salario: S/. No Especificado | Empresa: ConSol Partners

Senior Analog Design Engineer

Schematic/Layout), analog circuit simulation (Spectre/ADE), and digital RTL design (SystemVerilog). · Nice...

Lugar: Santa Clara, CA | 24/01/2026 23:01:38 PM | Salario: S/. No Especificado | Empresa: UST

FPGA Design Verification Engineer

benches using industry-standard verification methodologies (e.g., UVM, System Verilog, RTL). · Write and debug test cases...: · Strong understanding of FPGA, ASIC, RTL design principles and architectures. · Proficiency in System Verilog and UVM verification...

Lugar: Mountain View, CA | 24/01/2026 21:01:06 PM | Salario: S/. $101000 - 152000 per year | Empresa: UST
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