production. For example, candidate will participate in digital system architecture, block- and system-level RTL design/coding... of digital IC circuit design in an HDL synthesis environment Ability to develop RTL code and understand how RTL will map to gate...
Lugar:
Austin, TX | 18/03/2026 18:03:22 PM | Salario: S/. $129400 - 247800 per year | Empresa:
Skyworks: Full chip/block level architecture, RTL design and implementation Emulation, modelling, simulation, silicon testing...
Lugar:
Hillsboro, OR | 05/03/2026 03:03:57 AM | Salario: S/. $129400 - 247800 per year | Empresa:
Skyworks will be as a contributor to architecture and design in digital, including: Full chip/block level architecture, RTL design and implementation...
Lugar:
Hillsboro, OR | 04/03/2026 18:03:38 PM | Salario: S/. $129400 - 247800 per year | Empresa:
Skyworks Verification skills such as UVM testbench architecture, development and debug Strong RTL and Testbench debug skills Experience...
(Verilog coding, RTL synthesis, logic simulation, place and route) Proficient knowledge in memory cell test flow. Layout...
Lugar:
San Jose, CA | 27/03/2026 02:03:31 AM | Salario: S/. $116000 - 246000 per year | Empresa:
Micron architecture specifications for new features. Support the creation of schematics and/or RTL blocks Define best known design... and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate level) verification...
Lugar:
San Jose, CA | 26/03/2026 03:03:48 AM | Salario: S/. $116000 - 246000 per year | Empresa:
Micron. We are looking for a hardware micro-architects and RTL designers to develop Adreno GPU for Qualcomm Snapdragon compute platforms across the..., and automotive solutions. What you will be doing : Micro-architect and design RTL for blocks and modules of Adreno GPU...
microarchitecture design and implementation teams. The successful candidate will possess basic understanding of RTL design and ASIC... design flow from RTL to GDS such as synthesis, static timing analysis, formal verification, physical design, ECO generation...
Lugar:
San Diego, CA | 03/03/2026 03:03:03 AM | Salario: S/. $161800 - 242600 per year | Empresa:
Qualcomm. Additional Job Description Job Description: Synthesize the Verilog RTL and create models and compile them to emulators... to improve the area/performance of the synthesized FPGA RTL. Work on third-party IP integration and system-level debugging...
Lugar:
San Diego, CA | 03/03/2026 03:03:42 AM | Salario: S/. $161800 - 242600 per year | Empresa:
Qualcomm such as RTL designer, architecture, design verification, compiler, driver, silicon implementation, and post-silicon teams...
Lugar:
San Diego, CA | 03/03/2026 03:03:11 AM | Salario: S/. $161800 - 242600 per year | Empresa:
Qualcomm