Principal DSP Engineer

and digital designers. Create DSP and FEC hardware block specifications appropriate for RTL implementation. Perform research...

Lugar: Santa Clara, CA | 27/11/2025 22:11:50 PM | Salario: S/. $154240 - 231000 per year | Empresa: Marvell

DSP Architecture System Modeling Engineer

influence architecture, DSP/RTL design, validation, and customer applications. Ideal candidates excel in C/C++ DSP... blocks to isolate issues and unexpected behaviors. Reproduce complex edge cases and support other DSP and RTL engineers...

Lugar: Hudson Valley, NY | 13/12/2025 23:12:37 PM | Salario: S/. $155900 - 230770 per year | Empresa: Marvell

Principal CAD Engineer

communication skills Ability to run the following tasks is a plus: RTL to gates, and gates-to-gates equivalence checking Chip...

Lugar: Santa Clara, CA | 09/01/2026 03:01:43 AM | Salario: S/. $146850 - 220000 per year | Empresa: Marvell

Digital IC Principal Design Engineer

. What You Can Expect Oversee a team of engineers to develop and verify RTL design for CPU subsystems, co-processor/accelerator..., and enhancing the current IP. Responsibilities include: Define VLSI architecture. Implement RTL design. Verify design...

Lugar: Santa Clara, CA | 03/12/2025 01:12:29 AM | Salario: S/. $146850 - 220000 per year | Empresa: Marvell

Senior FPGA Development Engineer, Bespoke Solutions

for each government agency for which they perform AWS work. 10012 Key job responsibilities - Develop custom RTL and integrate... with custom hardware. You will debug RTL in simulation, synthesize and implement ensuring it meets timing and performance...

Lugar: Arlington, VA | 11/12/2025 01:12:01 AM | Salario: S/. $159200 - 215300 per year | Empresa: Amazon