Design for Test Engineering Intern - Bachelor's Degree

will be design verification, at block and full-chip, of DFT IP inserted at RTL level. This verification effort is UVM based... DFT RTL is added into a design. You will have the opportunity to gain experience in DFT architecture given the requirement...

Lugar: Boise, ID | 14/12/2025 02:12:06 AM | Salario: S/. $28 - 55 per hour | Empresa: Marvell

RTL Design Engineer

module. RTL design experience with multi-clock, high frequency designs, low latency, low power & high performance... blocks. RTL development using best industry practices. Optimize design for key metrics like Area, Power, Performance...

Lugar: San Jose, CA | 14/12/2025 02:12:56 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

DSP Architecture System Modeling Engineer

influence architecture, DSP/RTL design, validation, and customer applications. Ideal candidates excel in C/C++ DSP... blocks to isolate issues and unexpected behaviors. Reproduce complex edge cases and support other DSP and RTL engineers...

Lugar: Hudson Valley, NY | 14/12/2025 01:12:37 AM | Salario: S/. $155900 - 230770 per year | Empresa: Marvell