Senior Silicon Application Engineer (Packaging Design)

-related field Experience with Advanced EDA Tool Experience with Multi-die/3DIC Platform Tools: Cadence Integrity, Synopsys.../Innovus, Allegro (APD/SiP), Siemens Mentor Xpedition, Synopsys Fusion Compiler Experience with Verification Tools: Siemens...

Lugar: Chandler, AZ | 10/01/2026 18:01:44 PM | Salario: S/. No Especificado | Empresa: Intel

Design Engineer

Science or equivalent experience Preferred Qualifications: Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence...

Lugar: Sunnyvale, CA | 10/01/2026 18:01:16 PM | Salario: S/. No Especificado | Empresa: Aditi Consulting

Sr. Silicon Design Verification Engineer

such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including... with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor...

Lugar: San Jose, CA | 08/01/2026 03:01:49 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Principal Applications Engineer

design and verification (e.g., Cadence, Synopsys). Experience with lab equipment for signal integrity analysis and debugging...

Lugar: Santa Clara, CA | 08/01/2026 00:01:28 AM | Salario: S/. $143200 - 214500 per year | Empresa: Marvell