ASIC Design Engineer

(Python, Perl, TCL, shell programming) Experience with Synopsys Design Constraints (SDC) At Cisco we connect...

Lugar: San Jose, CA | 08/11/2024 18:11:12 PM | Salario: S/. $133300 - 186800 per year | Empresa: Cisco Systems

Test Timing Engineer

/capture and BIST. Prior working experience with SDC debugging & STA tools: Synopsys GCA/TCM/Primetime, Cadence CCD/Tempus...

Lugar: San Jose, CA | 08/11/2024 18:11:25 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

ASIC STA Engineer

(or other equivalent field) with 5+ years of related work experience. Prior experience using Synthesis Tools: Synopsys DC/DCG/FC. Prior... experience in Static Timing Analysis & ECO: Synopsys Primetime/Cadence Tempus. Prior experience with scripting such as TCL, Perl...

Lugar: San Jose, CA | 08/11/2024 18:11:37 PM | Salario: S/. $133300 - 186800 per year | Empresa: Cisco Systems

Senior FW Engineer

will have experience in: Synopsys ARC Processors, Risc-V, ARM Architectures C/C++, Python, Threading, MultiCore GIT/GITHub, Jira...

Lugar: Irvine, CA | 07/11/2024 18:11:29 PM | Salario: S/. No Especificado | Empresa: Western Digital

Principal Applications Engineer

design and verification (e.g., Cadence, Synopsys). Experience with lab equipment for signal integrity analysis and debugging...

Lugar: Santa Clara, CA | 07/11/2024 00:11:30 AM | Salario: S/. $137510 - 206000 per year | Empresa: Marvell