Senior Director EDA IT
Management & Procurement: Manage strategic relationships with key EDA software vendors (e.g., Synopsys, Cadence, Siemens EDA...
Lugar: Texas | 23/01/2026 22:01:52 PM | Salario: S/. No Especificado | Empresa: GlobalFoundries
Summer Intern - Digital Design Engineer
Processing (DSP) concepts. Proficiency in Verilog and Synopsys-based design flows. Experience with Matlab for algorithm...
Lugar: Austin, TX | 23/01/2026 19:01:42 PM | Salario: S/. No Especificado | Empresa: Cirrus Logic
ASIC Design Engineer
with EDA tools from Cadence, Mentor, and Synopsys Familiarity with version control systems like git Familiarity with Linux...
Lugar: Austin, TX | 23/01/2026 18:01:25 PM | Salario: S/. No Especificado | Empresa: Ericsson
Principal Static Timing Analysis (STA) Engineer – SoC Design
with advanced timing concepts: SI, CDC, LVF, POCV, etc. Proficiency in STA tools (e.g., Synopsys PrimeTime), scripting, and UNIX...
Lugar: Westborough, MA | 22/01/2026 22:01:13 PM | Salario: S/. $165000 - 244200 per year | Empresa: Marvell
Senior ASIC Timing Engineer
). Expertise and in-depth knowledge of industry standard EDA tools (Synopsys PrimeTime or Cadence Tempus). Proficiency in Python...
Lugar: Westford, MA | 22/01/2026 02:01:43 AM | Salario: S/. No Especificado | Empresa: Nvidia
Mechanical Engineer
. Deliver innovative solutions using Ansys and Synopsys simulation tools for a diverse customer base, collaborate with industry... solutions using Ansys and Synopsys tools Confidential Placement 🔠This role is a confidential placement for a leading...
Lugar: Tulsa, OK | 22/01/2026 02:01:35 AM | Salario: S/. $70000 - 90000 per year | Empresa: Top Engineer
Senior Design Engineer (SoC RTL)
off checks (LINT, CDC, RDC, LEC, UPF) Experience with Synopsys VCS or Cadence RTL simulator, Design Complier (DC) or RTL...
Lugar: San Diego, CA | 21/01/2026 23:01:34 PM | Salario: S/. No Especificado | Empresa: NXP Semiconductors
Sr Principal GaN Modeling Engineer
(e.g., Keysight ADS, Cadence AWR/Spectre, Synopsys, Silvaco) to perform simulations, analyze data, and validate model...
Lugar: Apopka, FL | 21/01/2026 23:01:01 PM | Salario: S/. No Especificado | Empresa: Qorvo
SOC IP Methodology Engineer - Custom SOC
vendors such as Cadence, Synopsys, Mentor (CDC, LP Checks, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler...
Lugar: Santa Clara, CA | 21/01/2026 19:01:09 PM | Salario: S/. No Especificado | Empresa: Nvidia
Senior Engineer, Digital Design Engineering
, scan pattern debugging Familiarity with Cadence and Synopsys design tools Experience debugging ICs and associated...
Lugar: Edinburgh - Freer, TX | 21/01/2026 18:01:05 PM | Salario: S/. No Especificado | Empresa: Analog Devices