Analog Layout Design Engineer

with Cadence Virtuoso Layout Editor or Synopsys Custom-Compiler is preferred. Responsibilities: Own and execute the layout...

Lugar: USA | 03/06/2026 17:06:24 PM | Salario: S/. $70 - 75 per hour | Empresa: Cynet Systems

Lead ASIC DFT Engineer

, JTAG, boundary scan, and silicon debug. Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools. Proven...

Lugar: USA | 03/06/2026 17:06:18 PM | Salario: S/. No Especificado | Empresa: ITMC Systems, Inc

Senior DFT Engineer (Einfochips)

and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion... Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch...

Lugar: USA | 03/06/2026 02:06:32 AM | Salario: S/. No Especificado | Empresa: Arrow Electronics