of experience with Cadence and/or Synopsys tools for Static Timing Analysis 4 years of experience in static timing analysis, noise...
in SystemVerilog and UVM verification methodology. Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS...
behavioral model verification Hands-on knowledge of standard industry EDA tools - Synopsys/Cadence Experienced with GLS...
and Route, Timing Analysis, and Physical Verification tools from Synopsys, Cadence, like ICC2, Fusion Compiler, DSO.AI, Innovus...
-speed interfaces) Proficiency in industry-standard simulation and design tools (e.g., Cadence, Synopsys) and programming...
design and RTL development (SystemVerilog, Verilog). Familiarity with SoC design flows and tools (e.g., Synopsys, Cadence...
and CMM model creation is nice to have Familiarity with entire VLSI design flow and tools (Cadence/Synopsys/Mentor...