DMTS Digital Design Engineer / Chip Lead
/ Genus) and guide optimization for PPA targets across all design blocks. IP Management: Define interfaces between PHY... with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus...
Lugar: Minneapolis, MN | 29/04/2026 21:04:57 PM | Salario: S/. No Especificado | Empresa: Micron