Mid-level Physical Design Engineer CPU
(genus/innovus) Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon...
Lugar: Hillsboro, OR | 10/08/2026 02:08:25 AM | Salario: S/. No Especificado | Empresa: Intel
Senior Physical Design Engineer (CPU)
to GDS methodologies and formal equivalence Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus...
Lugar: Hillsboro, OR | 09/08/2026 18:08:14 PM | Salario: S/. No Especificado | Empresa: Intel
Static Timing Analysis (STA) Engineer – (Lead or Senior)
(or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis Ability to work with large...
Lugar: El Segundo, CA - Los Angeles, CA | 07/08/2026 23:08:46 PM | Salario: S/. $146200 - 197800 per year | Empresa: Boeing
Physical Design Engineer, Synthesis and Implementation
, Cadence Genus, or comparable synthesis tools. Hands-on experience with synthesis constraints, timing analysis, QoR...
Lugar: Westford, MA | 02/08/2026 01:08:01 AM | Salario: S/. $116000 - 189750 per year | Empresa: Nvidia
Silicon Design Engineer
, placement, CTS, routing, timing closure, and physical signoff using industry-standard tools (Cadence Genus/Innovus...
Lugar: San Jose, CA | 31/07/2026 19:07:26 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices
Physical Design Engineer - Block Level, Subsystem Implementation
closure on advanced process nodes (5nm and below) Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler...
Lugar: Austin, TX | 30/07/2026 23:07:55 PM | Salario: S/. No Especificado | Empresa: Etched
Sr. DFT Engineer
Xcelium Cadence Genus Strong understanding of the ASIC development lifecycle from design through manufacturing. Preferred..., Tessent, Xcelium, Genus, ASIC, SoC, Post-Silicon Validation, Silicon Debug, Yield Analysis, Semiconductor Design. Experience...
Lugar: San Jose, CA | 30/07/2026 19:07:23 PM | Salario: S/. No Especificado | Empresa: Actalent
Contract Hardware Engineer Mid
EDA exposure: Design compiler, PrimeTime, Tempus, Genus, Multi-Node Design: Experience working with 16nm, 7nm...
Lugar: San Jose, CA | 29/07/2026 21:07:08 PM | Salario: S/. No Especificado | Empresa: US Tech Solutions
ASIC DTCO, Timing and Technology Engineer
, FC Place and Route, Genus and Innovus, The candidate will be responsible for design implementation of multiple blocks...
Lugar: San Diego, CA | 29/07/2026 17:07:25 PM | Salario: S/. No Especificado | Empresa: Qualcomm
Senior Staff Digital Design Engineer
-aware design methodologies Proficiency in Python, Tcl, Perl, or Shell scripting Experience with Xcelium, Genus, SpyGlass...