STA Engineer
designs, UPF). Hands‑on experience with: Synopsys Prime Time Synopsys Design Compiler / Cadence Genus Preferred...
Lugar: Santa Clara, CA | 09/07/2026 00:07:08 AM | Salario: S/. No Especificado | Empresa: Qualcomm
Sr Principal Application Engineer
, and Logical Equivalence Checking Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus...
Lugar: San Jose, CA | 08/07/2026 21:07:08 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
Digital IC Design Engineer
with synthesis and static timing analysis tools (Synopsys Design Compiler, Cadence Genus, or equivalent) Experience with low-power...
Lugar: Dallas, TX | 30/06/2026 00:06:38 AM | Salario: S/. No Especificado | Empresa: Texas Instruments
Sr Principal Application Engineer
, and customer communication skills. Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus...
Lugar: San Jose, CA | 26/06/2026 02:06:12 AM | Salario: S/. $123200 - 228800 per year | Empresa: Cadence Design Systems
Lead ASIC Design Engineer
: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static...
Lugar: San Jose, CA | 20/06/2026 22:06:35 PM | Salario: S/. No Especificado | Empresa: Broadcom
Infra Systems Physical Architect
Sync Clock Routing Formal verification experience Power domain analysis experience Design Compiler/Fusion Compiler/Genus...
Lugar: San Diego, CA | 20/06/2026 02:06:54 AM | Salario: S/. No Especificado | Empresa: Qualcomm
Research & Development Intern – Citrus Innovation Center
Learning & Development Develop foundational knowledge the genus citrus, citrus processing, and the composition of citrus...
Lugar: Florida | 18/06/2026 17:06:08 PM | Salario: S/. No Especificado | Empresa: International Flavors & Fragrances
Principal Product Engineer, Synthesis
products. Job responsibilities: Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis..., Performance & Area (PPA) for latest digital ASICs Understand the internal flow within the Genus for newly developed features...
Lugar: San Jose, CA | 16/06/2026 21:06:41 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
Senior Implementation Methodology Engineer
-and-route tools from Synopsys (DC/FC, ICC2, PrimeTime) and/or Cadence (Genus, Innovus, Tempus). Prior experience in data...
Lugar: Santa Clara, CA | 14/06/2026 00:06:17 AM | Salario: S/. No Especificado | Empresa: Nvidia
FPGA Engineer Engineer (eInfochips)
, Questa CDC, Fusion Compiler, Design Compiler, Genus. Proficiency with UPF (Low power intent) Proficiency in clock...
Lugar: San Jose, CA | 13/06/2026 22:06:38 PM | Salario: S/. No Especificado | Empresa: Arrow Electronics