logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers... from netlist to GDSII on advanced nodes and complex designs. Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus...
and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate level) verification... at block, subsystem, and full chip level Facilitate netlist bring up to achieve basic functionality Responsible...
and netlist level Power analysis. Perform post-processing and scripting on report log files for format conversion, data analysis...
and effective chip layout. Convert RTL code into a gate-level netlist, ensuring the design meets area, power, and performance...
best known design and verification practices and communicate them to the department Perform RTL and synthesized netlist (gate... level) verification at block, subsystem, and fullchip level Facilitate netlist bring up to achieve basic functionality...
such as Python, Tcl, and SystemVerilog. Responsibilities: Perform PPA optimization with Fusion compiler. Conduct RTL and netlist...
, netlist bring‑up, and debug by using data‑driven methods to identify failure trends, corner cases, and root causes...
Handling (CDH) team. This role involves overseeing electrical interfaces through netlist management, driving vehicle...
in leading and implementing high performance subsystems from specification to final netlist. Knowledge of Computer Architecture...
ever. Responsibilities Lead end‑to‑end physical design for High Bandwidth Memory (HBM) base and memory dies from netlist through GDSII...