CAM Engineer
outputs for machine on the production floor. Perform netlist extraction and compare again the original design for data...
Lugar: Bastrop, TX | 14/10/2026 18:10:21 PM | Salario: S/. $50 - 80 per hour | Empresa: Actalent
ASIC Verification Engineer
, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex...
Lugar: Sunnyvale, CA | 13/10/2026 22:10:58 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise
NPI Engineer
and checking symbol validity, generating, checking netlist and identify design rule errors. Checks OrCAD schematics for symbol... validity, design rule errors, netlist validity. Checks BOMs for accuracy, RoHS compliance, obsolete parts. Generate assembly...
Lugar: Pleasanton, CA | 13/10/2026 19:10:17 PM | Salario: S/. No Especificado | Empresa: AMETEK
IC Layout Co-op (Summer/Fall 2027)
a schematic/netlist-driven CAD layout process A self-starter and team player with ability to learn on the job Experience using...
Lugar: Cedar Rapids, IA | 13/10/2026 17:10:19 PM | Salario: S/. No Especificado | Empresa: Skyworks
Scientist, Electrical Engineer
from RTL design through structural netlist timing closure including CDC and UPF. 5+ years' experience in schematics design...
Lugar: Yorba Linda, CA | 10/10/2026 02:10:08 AM | Salario: S/. $153000 per year | Empresa: L3Harris Technologies
Senior ASIC Physical Design Engineer
, and implement fixes to achieve performance, power, and area objectives. Perform synthesis, netlist quality checks, and formal... with one or more of the following: Static timing analysis and timing signoff Timing constraints and validation Synthesis and netlist...
Lugar: Fort Collins, CO | 09/10/2026 23:10:22 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise
Sr. SoC Power Engineer, Annapurna Labs - Cloud Scale Machine Learning
and estimating power at every stage of the design from early RTL to final netlist and by driving ways to reduce power consumption... stages of design (RTL to gate level netlist) - Develop and maintain dashboards for power rollups - Work with designers...
Lugar: Cupertino, CA | 09/10/2026 17:10:59 PM | Salario: S/. No Especificado | Empresa: Amazon
Sr. ASIC Design Engineer
, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex...
Lugar: Roseville, CA | 09/10/2026 17:10:56 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise
EDA/CAD Software Engineer, Staff
in the areas of RTL Synthesis (System Verilog ->Netlist), Clock Tree Optimization, Exposure to VLSI design concepts...
Lugar: San Diego, CA | 09/10/2026 00:10:36 AM | Salario: S/. No Especificado | Empresa: Qualcomm
SOC Engineering, Senior Engineer
logic for synthesis, and support timing closure from netlist through signoff Implement standard interface protocols...
Lugar: Gilbert, AZ | 08/10/2026 22:10:44 PM | Salario: S/. No Especificado | Empresa: Synopsys