Sr Physical Design Engineer
Evaluate feasibility of architectural features through back end implementation Deliver a synthesized netlist to ASIC...
Lugar: Austin, TX | 06/11/2025 18:11:26 PM | Salario: S/. No Especificado | Empresa: Ericsson
SoC Physical Design Engineer, PnR
partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology. Description Work.... • Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. • Timing, physical and electrical...
Lugar: Sunnyvale, CA | 06/11/2025 03:11:58 AM | Salario: S/. No Especificado | Empresa: Apple
ASIC Engineer, Physical Design
with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System...
Lugar: Austin, TX - Sunnyvale, CA | 06/11/2025 02:11:57 AM | Salario: S/. No Especificado | Empresa: Meta
SoC Physical Design Engineer, PnR
partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology... architecture and drive physical aspects early in the design cycle. • Completing netlist to GDS2 implementation for partition...
Lugar: Sunnyvale, CA | 06/11/2025 01:11:33 AM | Salario: S/. $126800 - 190900 per year | Empresa: Apple
SoC Physical Design Engineer, PnR
partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology. Description Work.... • Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. • Timing, physical and electrical...
Lugar: Sunnyvale, CA | 05/11/2025 23:11:28 PM | Salario: S/. No Especificado | Empresa: Apple
SoC Physical Design Engineer, PnR
partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology. Description Work.... • Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. • Timing, physical and electrical...
Lugar: Sunnyvale, CA | 05/11/2025 22:11:34 PM | Salario: S/. No Especificado | Empresa: Apple
SoC Physical Design Engineer, PnR
partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology. Description Work.... • Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. • Timing, physical and electrical...
Lugar: Sunnyvale, CA | 05/11/2025 20:11:51 PM | Salario: S/. No Especificado | Empresa: Apple
RF/Analog Design/Functional Modeling and Verification Engineer – AI/ML Enhanced
and sequences. Maintain scripts for netlist release and programming instruction generation. Diagnose failed tests and manage...
Lugar: Santa Clara, CA | 04/11/2025 23:11:54 PM | Salario: S/. No Especificado | Empresa: Qualcomm
CPU Server Power Analysis Lead
vector plan and definition for comprehensive coverage of the CPUSS. Drive power analysis on RTL and Netlist using tools...
Lugar: Austin, TX | 01/11/2025 23:11:33 PM | Salario: S/. No Especificado | Empresa: Qualcomm
DFT IC Design Engineer
cycle experience in RTL/Netlist Excellent verbal and written communication skills Education and Experience Requirements...
Lugar: Colorado Springs, CO | 31/10/2025 01:10:44 AM | Salario: S/. $108000 - 172800 per year | Empresa: Broadcom