Design Engineer - Sensors

, RTL generation, and delivering a timing-closed netlist for layout. The successful candidate will work with architects... Teams Adherence to Qualcomm's processes for RTL and netlist releases Python automation, as well as enabling new...

Lugar: Santa Clara, CA | 17/01/2026 18:01:23 PM | Salario: S/. No Especificado | Empresa: Qualcomm

Senior ASIC Physical Design Engineer, Netlisting

-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects... such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist...

Lugar: Santa Clara, CA | 09/01/2026 02:01:12 AM | Salario: S/. No Especificado | Empresa: Nvidia

IC DESIGN ENGINEER

implementing chips from netlist to GDSii with good understanding of the technology elements as well as design flow in all stages...

Lugar: San Jose, CA | 18/12/2025 19:12:25 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

ASIC Design Engineer Staff

of our fast-paced chip design group, you will become an expert in building high-speed ASICs, from specifications to final netlist... skills in leading and implementing high performance modules from specification to final netlist. Knowledge of Computer...

Lugar: Sunnyvale, CA | 13/12/2025 20:12:25 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise

DFM Valor Engineer

Qualifications: Experience with scripting for automation (VBScript, Python). Familiarity with other EDA tools and basic netlist...

Lugar: Irvine, CA - Palo Alto, CA | 05/12/2025 22:12:03 PM | Salario: S/. No Especificado | Empresa: Rivian