Senior Design Engineer

and synthesized netlist (gate level) verification at block, subsystem, and fullchip level Facilitate netlist bring up to achieve...

Lugar: San Jose, CA | 07/08/2026 21:08:18 PM | Salario: S/. $116000 - 198000 per year | Empresa: Micron

HBM SoC Physical Design Engineer

logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers.... Required Qualifications Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs...

Lugar: Folsom, CA | 02/08/2026 02:08:57 AM | Salario: S/. $121000 - 205000 per year | Empresa: Micron