Senior ASIC Physical Design Engineer, Netlisting
-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects... such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist...
Lugar: Santa Clara, CA | 24/07/2026 18:07:24 PM | Salario: S/. No Especificado | Empresa: Nvidia