engineer will own RTL design from architecture through validation, working hands-on across the full FPGA development lifecycle..., and maintain FPGA RTL using Verilog/SystemVerilog and/or VHDL Support the full FPGA development lifecycle, including synthesis...
for implementation Implement design in RTL (VHDL) and perform module level simulations Perform Synthesis, Place and Route... (PAR) and Static Timing Analysis (STA) Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC...
of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading... and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve...
++, developing test code in parallel with RTL and applying constrained-random testing, coverage-driven verification, and assertion...
verification scripts to improve FPGA verification efforts. Cross discipline collaboration with RTL Designers, Systems Architects...