Staff GenAI Engineer - Silicon Design
to design automation. Knowledge of Synopsys, Cadence, Siemens, or equivalent EDA platforms. Proven collaboration...
Lugar: San Jose, CA | 02/09/2026 18:09:06 PM | Salario: S/. No Especificado | Empresa: Micron
Lead ASIC Design Engineer
from industry leaders such as Cadence, Synopsys, and Siemens Experience designing and deploying ASICs on advanced semiconductor...
Lugar: Bedford, MA | 01/09/2026 22:09:30 PM | Salario: S/. No Especificado | Empresa: Mitre
Lead FPGA Design Engineer
suites from industry leaders such as Cadence, Synopsys, Siemens, AMD (Xilinx), and Intel (Altera). Experience designing...
Lugar: Bedford, MA | 01/09/2026 18:09:28 PM | Salario: S/. No Especificado | Empresa: Mitre
Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
with package layout tools such as Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, or equivalent - Deep understanding...
Principal Signal Integrity Engineer – R&D Networking Platforms
, statistical, BER, and electromagnetic analysis. Deep expertise with industry-standard tools such as Synopsys HSPICE, Keysight ADS...
Lugar: Roseville, CA | 29/08/2026 18:08:38 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise
Lead Engineer
in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA...
Lugar: Santa Clara, CA | 29/08/2026 17:08:29 PM | Salario: S/. $65 - 75 per hour | Empresa: Quest Global
ASIC Engineer- CAD
in Python, Perl, TCL, or shell programming. Preferred Qualifications: Experience with Synopsys Design Constraints (SDC...
Lugar: San Jose, CA | 28/08/2026 17:08:42 PM | Salario: S/. No Especificado | Empresa: Cisco Systems
Senior Backend Design Automation Engineer — New Process Node Enablement
and qualification. 8+ years of professional experience using industry-standard Back-End EDA tools, including tools from Synopsys...
Lugar: San Jose, CA | 28/08/2026 02:08:41 AM | Salario: S/. No Especificado | Empresa: Altera
ASIC & FPGA Design Engineer Stf - E4
‑domain crossing and timing‑closure challenges with Synopsys VCS and Xilinx Vivado tools. Performing place‑and‑route, timing... such as Synopsys VCS \- Proficiency with timing analysis, clock-domain crossing, signal integrity, and IP integration \- Experience...
Lugar: Orlando, FL | 28/08/2026 00:08:15 AM | Salario: S/. No Especificado | Empresa: Lockheed Martin
Sr Design Verification Engineer, DRAM
and simulation using SPICE and Verilog Knowledge of digital and analog circuit design methodologies and tools such as Synopsys...