Design For Test Engineer (Einfochips Inc)

implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass... Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools...

Lugar: Mountain View, CA | 08/04/2026 19:04:46 PM | Salario: S/. No Especificado | Empresa: Arrow Electronics

Design For Test Engineer IV (IC)

and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion... Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch...

Lugar: San Jose, CA | 02/04/2026 22:04:55 PM | Salario: S/. $112200 - 170500 per year | Empresa: Arrow Electronics

Principal Engineer

\. Cadence layout tools, including Innovus or Tempus or Synopsys, including ICC2 or PrimeTime;7\. PDN design and evaluation...

Lugar: Richardson, TX | 31/03/2026 19:03:51 PM | Salario: S/. No Especificado | Empresa: Micron