to JEDEC standards (DDR4/DDR5/LPDDR5/LPDDR6) Using simulators (e.g., VCS) and emulators (e.g., Synopsys ZeBu, Cadence... (especially for LPDDR5 with deeper power states) Using hardware description languages (HDL) and simulators (like Synopsys VCS...
and simulation. Proficiency with FPGA synthesis and partitioning tools (e.g., Synplify, Vivado). Experience with Synopsys HAPS.... Skills: Verilog, VHDL, System Verilog, Xilinx FPGA, HAPS, Vivado, C/C++ Synopsys ZeBu, Cadence Palladium/Protium...
. Required Skills: Verilog, VHDL, SystemVerilog, Xilinx FPGA, HAPS, Vivado, C/C++, Synopsys ZeBu, Cadence Palladium/Protium, Mentor... (e.g., Synplify, Vivado) Experience working with Synopsys HAPS prototyping platforms Solid understanding of SoC bring-up...
and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion... Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch...
-standard EDA tools for design and simulation such as Cadence, Synopsys, Ansys etc. Basic scripting and automation using PERL...
closure;collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA...
closure;collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA...
Experience setting up and debugging simulations using Cadence/Synopsys toolchains Familiarity with DC-DC buck converter concepts...
and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion... Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch...
architectures Familiarity with version control software (GIT). Experience with Synopsys simulators...