Senior Test Application Engineer
and tester-resident software. Familiarity with EDA tools (Siemens, Synopsys, Cadence) is a plus. Demonstrated ability to plan...
Hardware Design Engineer - Santa Clara, CA
boards, Synopsys HAPS platforms etc Experience with Xilinx Versal ACAP or UltraScale+ devices Knowledge of FPGA synthesis...
Lugar: Santa Clara, CA | 16/05/2026 20:05:15 PM | Salario: S/. No Especificado | Empresa: Sunrise Systems
HBM SoC RTL Design Engineer
considerations. Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens. Programming or scripting experience (e.g...
Lugar: Folsom, CA | 15/05/2026 22:05:53 PM | Salario: S/. No Especificado | Empresa: Micron
Senior Testchip SoC Physical Design Engineer (Integration & Methodology)
like Cadence Virtuoso Suite or Synopsys Custom Compiler Design rules and layout constraints in advanced semiconductor processes...
Lugar: Hillsboro, OR | 15/05/2026 21:05:38 PM | Salario: S/. No Especificado | Empresa: Intel
SoC Timing (Static Timing Analysis/STA) Engineer, HBM
across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys... on multiple tape-outs at 5nm or below. Deep expertise with industry-standard static timing analysis tools such as Synopsys...
Lugar: Richardson, TX | 15/05/2026 20:05:25 PM | Salario: S/. No Especificado | Empresa: Micron
Senior Engineer Design Verification Engineering
simulator suite, Synopsys VCS or equivalent. DE driving metric-driven verification, including specifying, developing...
Lugar: Beaverton, OR | 15/05/2026 19:05:11 PM | Salario: S/. $119475 - 163200 per year | Empresa: Analog Devices
Senior Engineer, Design Verification Engineering
simulator suite, Synopsys VCS or equivalent. DE driving metric-driven verification, including specifying, developing...
Lugar: Dallas, TX | 15/05/2026 19:05:25 PM | Salario: S/. $117042 - 165615 per year | Empresa: Analog Devices
Senior SOC Physical Design Engineer, HBM
, clocking concepts, and Synopsys Design Constraints (SDC). Working knowledge of power intent methodologies including Unified...
Lugar: Richardson, TX | 15/05/2026 18:05:58 PM | Salario: S/. No Especificado | Empresa: Micron
SOC Timing Analysis (STA) Engineer ,HBM
, and voltage and temperature conditions. Develop, maintain, and validate comprehensive Synopsys Design Constraints (SDC... such as Synopsys PrimeTime and/or Cadence Tempus, including configuration of analysis modes, corner libraries, and sign-off decks...
Lugar: Richardson, TX | 15/05/2026 18:05:31 PM | Salario: S/. No Especificado | Empresa: Micron
Senior ASIC Verification Engineer
, coverage methodologies, and testbench architecture Experience working with leading EDA toolchains (e.g., Cadence, Synopsys...
Lugar: San Jose, CA | 15/05/2026 17:05:14 PM | Salario: S/. $150000 - 230000 per year | Empresa: 4 Staffing Corp - Client Jobs