Chip Power Integrity Engineer
and CMM model creation is nice to have Familiarity with entire VLSI design flow and tools (Cadence/Synopsys/Mentor...
Lugar: San Jose, CA | 06/11/2025 20:11:35 PM | Salario: S/. No Especificado | Empresa: Broadcom
Integration Engineer
design and RTL development (SystemVerilog, Verilog). Familiarity with SoC design flows and tools (e.g., Synopsys, Cadence...
Lugar: Santa Clara, CA | 06/11/2025 18:11:29 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple
Chiplet Physical Design Engineer
/DRC. Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.) NVIDIA has some of the most forward...
Lugar: Westford, MA | 04/11/2025 23:11:53 PM | Salario: S/. No Especificado | Empresa: Nvidia