experience with Cadence Innovus, Synopsys Fusion Compiler, and modern RTL‑to‑GDS flows. This role focuses on developing scalable... or physical design methodology. Strong expertise in: Cadence Innovus place and route, and/or Synopsys Fusion Compiler...
utilizing RTL optimization strategies. Conduct formal verification of design with Synopsys Formality / Cadence Conformal...
(e.g., PDF Solutions, Synopsys YieldExplorer, or Cadence Clarity). Additional Job Description: Compensation...
or communications applications is a strong plus Experience with EDA tools (Cadence, Synopsys, or Mentor Graphics) is a prerequisite...
Virtuoso and Synopsys Verification tools to perform layout design, verification, and integration. Drive floorplanning...
Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework.... Proficient with CDC, RDC. Formal EDA. Proficient in VHDL. Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado...
and languages such as Synopsys VCS and SystemVerilog -Strong understanding of digital design principles, including timing analysis...
, microprocessors, and chip I/O is advantageous. Proficiency with Synopsys Design Compiler, timing closure methodologies, and formal...
is a plus. Simulation Tools: Proficiency with simulation and design tools such as SPICE, Cadence, Synopsys, Mentor Graphics, and layout...
, Synopsys, and/or Mentor) Foundational knowledge of digital logic and timing considerations Strong written and verbal...