Principal ASIC Design Engineer

. ### Synthesis & Timing Execute logic synthesis (Synopsys Design Compiler or Cadence Genus) and drive optimization toward PPA... practices Hands-on experience with logic synthesis (Design Compiler or Genus) and static timing analysis (PrimeTime or Tempus...

Lugar: Boise, ID | 26/09/2026 01:09:24 AM | Salario: S/. No Especificado | Empresa: Micron

Consulting Engineer 3: 26

tool sets, Xcelium, Genus, and Tempus/Primetime. At least one project with hands-on post-silicon debug of DFT patterns...

Lugar: Carlsbad, CA | 12/09/2026 17:09:55 PM | Salario: S/. $70 - 75 per hour | Empresa: Akraya