Principal Design Engineer
(GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior. Sign-off: Define the...
Lugar: Austin, TX | 03/10/2026 01:10:20 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
Lead Design Engineer
. Gate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior. Sign-off...
Lugar: Austin, TX | 02/10/2026 23:10:13 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
Lead Design Engineer
. Gate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior. Sign-off...
Lugar: Austin, TX | 02/10/2026 20:10:31 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
Principal Design Engineer
(GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior. Sign-off: Define the...
Lugar: Austin, TX | 02/10/2026 18:10:03 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
Staff Package Design Engineer
, yield, and long-term reliability. Manage the package design cycle, including schematic creation, netlist import, footprint... design rules, including DRC, LVS, connectivity, and netlist verification requirements. Support Engineering Change Order...
Lugar: Tempe, AZ | 02/10/2026 17:10:50 PM | Salario: S/. No Especificado | Empresa: Renesas Electronics
Engineering Intern - ASIC DFT (Spring 2027 Co-Op)
setup using Post -DFT RTL/Netlist. Run simulation using the test list or patterns. Memory Built-in Self test[MBIST...
Lugar: Palo Alto, CA | 01/10/2026 22:10:45 PM | Salario: S/. $45 - 51 per hour | Empresa: Rivian
3D IC and SoC CAD ENGINEER
environments for industry-leading methodologies for 3D IC stack and advanced packaging design. Our flows encompass 3D netlist...
Lugar: Austin, TX | 01/10/2026 21:10:32 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices
Sr Principal Software Engineer, Innovus — Physical Synthesis & Optimization
, performance, area (PPA), and congestion. Work directly with large-scale layout and netlist data to build practical, highly...
Lugar: San Jose, CA | 01/10/2026 18:10:43 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
Staff Package Design Engineer
. Manage the package design cycle, including schematic creation, netlist import, footprint assignment, layout implementation..., connectivity, and netlist verification requirements. Support Engineering Change Order cycles, design updates, revision control...
Lugar: Tempe, AZ | 01/10/2026 17:10:17 PM | Salario: S/. No Especificado | Empresa: Renesas Electronics
Advanced Package Design Senior Staff Engineer
and electrical design activities, including floorplanning, netlist creation, and BGA map definition, while optimizing signal.... Experience with high-speed electronic packaging for digital and analog ICs, package floor planning, netlist, schematic and BGA...
Lugar: Santa Clara, CA | 01/10/2026 02:10:18 AM | Salario: S/. $141150 - 211400 per year | Empresa: Marvell