Staff Applications Engineer, HAV Solutions
, ProtoCompiler runtime debug tools, and protocol analyzers to troubleshoot RTL, netlist, timing, and hardware issues The Impact...
Senior Hardware Security Engineer
, evaluation, and/or research ASIC and/or FPGA design Netlist recreation of printed circuit boards and components using X-ray...
Lugar: Albuquerque, NM | 17/09/2026 22:09:26 PM | Salario: S/. No Especificado | Empresa: Mitre
Senior Principal ASIC Design Engineer
from product requirements and architecture through final netlist. You will work on complex, high-impact subsystems, collaborate... final netlist. Prior first-authored patents in networking or computer architecture are a plus. Proven technical...
Lugar: Roseville, CA | 16/09/2026 00:09:45 AM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise
SoC Physical Design Senior Manager, HBM
and physical verification engineers responsible for implementation of advanced HBM SoC logic/base die designs from netlist to GDSII... from netlist to GDSII on advanced nodes and complex designs. Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus...
Lugar: Folsom, CA | 12/09/2026 02:09:18 AM | Salario: S/. No Especificado | Empresa: Micron
Internship - Analog Mixed Signal Design
with Cadence tools for schematic creation, netlist generation, and simulation execution in analog or mixed-signal environments...
Lugar: El Segundo, CA | 08/09/2026 19:09:07 PM | Salario: S/. No Especificado | Empresa: Infineon
RGP - Advanced Mixed Signal Modeling Engineer
mixed-signal simulation workbenches in Cadence ADE Explorer and Xcelium and automate regression runs Schematic/Netlist...
Lugar: Andover, MA | 04/09/2026 01:09:42 AM | Salario: S/. $65000 - 90000 per year | Empresa: Infineon
Software Engineer II
of digital design flows, logic synthesis, formal methods, RTL-to-netlist verification, and semiconductor design methodologies...
Lugar: Austin, TX | 02/09/2026 22:09:54 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
ARM SoC Physical Design Engineer
hands-on MS/BSEE with breadth and depth in the areas below: MS/BSEE Expert handling of Verilog HDL Netlist and Physical...
Lugar: San Jose, CA | 29/08/2026 01:08:11 AM | Salario: S/. No Especificado | Empresa: Steinman Recruiting Associates
ASIC Design Engineer 2
, you will become an expert in building high-speed ASICs, from specifications to final netlist. You can pick and choose where you want to work...
Lugar: Sunnyvale, CA | 28/08/2026 02:08:42 AM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise
Staff Physical Design Engineer, HBM
in advanced memory products. This role spans backend implementation from Netlist to GDSII, with a strong focus on timing closure... and execute physical design implementation from synthesized netlist through GDSII, including floorplanning, placement, clock tree...
Lugar: Richardson, TX | 27/08/2026 23:08:22 PM | Salario: S/. No Especificado | Empresa: Micron