Senior FPGA Design Engineer

and control systems. Model signal processing path and algorithms in Matlab/Simulink or Python and port them to RTL being executed...

Lugar: Fremont, CA | 28/01/2026 20:01:02 PM | Salario: S/. No Especificado | Empresa: Lam Research

Senior ASIC Timing Engineer

with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create...

Lugar: Santa Clara, CA | 28/01/2026 19:01:52 PM | Salario: S/. No Especificado | Empresa: Nvidia

Formal Equivalence Checking Methodology Engineer

, and optimizing RTL verification methodologies - Logical Equivalence and RTL Lint, for our ground breaking VLSI designs. This role... is crucial in ensuring the functional equivalence of our designs throughout the design cycle, from RTL to GDSII! What you’ll...

Lugar: Santa Clara, CA | 28/01/2026 18:01:27 PM | Salario: S/. No Especificado | Empresa: Nvidia

FE Design Engineer

AND RESPONSIBILITIES: * This role serves as the technical bridge between RTL design and back-end physical implementation. Synthesis...

Lugar: Milpitas, CA | 28/01/2026 18:01:23 PM | Salario: S/. No Especificado | Empresa: SanDisk

Design Verification Engineer

, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design. Coordinate with RTL... with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity...

Lugar: Austin, TX | 28/01/2026 03:01:32 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

IC Design Engineer

with a focus on high-speed communication interfaces. Must have strong Logic Design, RTL coding (Verilog HDL) skills...

Lugar: San Jose, CA | 28/01/2026 03:01:12 AM | Salario: S/. No Especificado | Empresa: Broadcom