Sr. Silicon Design Engineer

interfaces/formats for simulation. Perform RTL design and debug of relevant blocks to realize the low power architecture... or Cadence Conformal Low Power;RTL design in Verilog or SystemVerilog;Low power digital design and analysis;SOC tools...

Lugar: San Jose, CA | 24/01/2026 23:01:33 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices