FPGA Design Verification Engineer

benches using industry-standard verification methodologies (e.g., UVM, System Verilog, RTL). · Write and debug test cases...: · Strong understanding of FPGA, ASIC, RTL design principles and architectures. · Proficiency in System Verilog and UVM verification...

Lugar: Mountain View, CA | 31/01/2026 22:01:01 PM | Salario: S/. $101000 - 152000 per year | Empresa: UST

DFT Design Engineer, Machine Learning Acceleration

efficient DFT solutions Perform RTL coding and Verification using Verilog/System Verilog Utilize industry standard DFT tools... experience developing STA constraints for DFT modes and working directly with PD teams to close timing - Experience with RTL...

Lugar: Austin, TX | 31/01/2026 22:01:21 PM | Salario: S/. No Especificado | Empresa: Amazon

Senior Digital Design Engineer

RTL language, verify the functionality, and follow up until completion of the product. ESSENTIAL JOB DUTIES... AND RESPONSIBILITIES: Understand product requirements, gather the relevant information, and develop a solution. Use RTL language...

Lugar: Laguna Hills, CA | 31/01/2026 21:01:35 PM | Salario: S/. No Especificado | Empresa: BrainChip, Inc.

ASIC Clocks Design Engineer - New College Grad 2026

of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team..., we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. Get involved in end-to-end cycle...

Lugar: Santa Clara, CA | 31/01/2026 21:01:52 PM | Salario: S/. $100000 - 166750 per year | Empresa: Nvidia

Senior Engineer, GPU Performance Architect (PPA)

, performance analysis and verification, waveform-level and RTL debugging, with curiosity for advancing performance and power... through prototyping, model-to-RTL correlation, and deep-dive validation—including simulation, waveform analysis using tools...

Lugar: San Jose, CA | 31/01/2026 18:01:35 PM | Salario: S/. No Especificado | Empresa: Samsung