ASIC Clocks Design Engineer - New College Grad 2026

of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team..., we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. Get involved in end-to-end cycle...

Lugar: Santa Clara, CA | 01/02/2026 03:02:17 AM | Salario: S/. $100000 - 166750 per year | Empresa: Nvidia

Senior ASIC Design Engineer

, or equivalent experience. 8+ years of build/RTL experience working on complex units in xbar/memory system. Highly proficient.... A deep understanding of ASIC flow including RTL, verification, logic synthesis, timing analysis, ECO, and post silicon debug...

Lugar: Santa Clara, CA | 01/02/2026 01:02:27 AM | Salario: S/. No Especificado | Empresa: Nvidia

Software Development Engineer II, Post Silicon Validation

, RTL design, design verification, firmware, and software teams to ensure our next-generation AI/ML accelerators meet the... networks, ML HW architecture, and/or CI/CD - Familiarity with the validation lifecycle from RTL simulation (SystemVerilog/UVM...

Lugar: Austin, TX | 01/02/2026 00:02:26 AM | Salario: S/. No Especificado | Empresa: Amazon