Interaction Design Intern
setup/hold timing violations. Collaborate with RTL, DFT, and backend design teams. Support low-power and high-performance...
Design Verification Engineer
, and close functional/code coverage Debug simulation failures and work closely with RTL designers to resolve issues Execute... checks, and work with UPF/CPF as needed Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design...
Lugar: Santa Clara, CA | 04/06/2026 17:06:35 PM | Salario: S/. No Especificado | Empresa: iFlow Inc
ASIC Engineering Technical Leader- DFT
in San Jose with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams... role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design...
Lugar: San Jose, CA | 04/06/2026 17:06:35 PM | Salario: S/. No Especificado | Empresa: Cisco Systems
Sr. FPGA Engineer, Direct to Device, Amazon Leo
with uArchitecture, RTL coding, FPGA optimization for timing & power, simulation, and validation Preferred Qualifications - 6+ years...
Lugar: Redmond, WA | 04/06/2026 02:06:33 AM | Salario: S/. No Especificado | Empresa: Amazon
Field Application Engineer – PowerPro
for RTL and gate-level power analysis and optimization. You will work closely with leading semiconductor customers to drive... Collaborate with R&D and Product teams to influence product enhancements Qualifications Required: Strong RTL design...
Lugar: California | 04/06/2026 02:06:45 AM | Salario: S/. No Especificado | Empresa: Siemens
Senior Technical Program Manager - VLSI
tracking, resource planning, and program health visibility across the full lifecycle—from Arch/RTL handoff through silicon...
Lugar: Santa Clara, CA | 04/06/2026 01:06:21 AM | Salario: S/. No Especificado | Empresa: Nvidia
Principal Product Engineer
track record of shipping designs or product improvements. â–¸ Expert-level understanding of the full RTL-to-GDSII flow... to Have â–¸ Experience with Cadence Joules RTL Power Solution, Voltus IC Power Integrity, or Innovus-Tempus integrated signoff flows...
Lugar: San Jose, CA | 04/06/2026 00:06:34 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
Memory Control Design Engineer
. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible...
Lugar: San Diego, CA | 03/06/2026 23:06:22 PM | Salario: S/. $98500 - 147700 per year | Empresa: Qualcomm
Microprocessor VLSI Physical Design Engineer
closely with RTL and physical designers across multiple sites to optimize power, performance, area, and schedule. Solve... Verilog RTL and make minor modifications for timing or power. Knowledge of digital circuits, high speed flops, synchronizers...
Lugar: Fort Collins, CO | 03/06/2026 23:06:10 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices
Senior DFX Power Methodology Engineer
for data analysis & insights. Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route...
Lugar: Santa Clara, CA | 03/06/2026 23:06:19 PM | Salario: S/. No Especificado | Empresa: Nvidia