Technical Program Manager- IP/PDK
leadership and communication — Partner routinely with Program/Project Management, Physical Design, Package / SI, RTL/Design...
leadership and communication — Partner routinely with Program/Project Management, Physical Design, Package / SI, RTL/Design...
, decomposition, and traceability. Develop RTL design code and simulation in VHDL, Verilog, and/or System Verilog. Develop Hardware... of experience. Experience writing RTL and test benches using VHDL, UVM, Verilog, or SystemVerilog. Experience with Linux (or Unix...
Perl, Ruby, Make, or the likes. Exposure to RTL design, software development, formal verification, or other related... components in SystemVerilog and UVM along with formal to achieve verification of the design. Coordinate with RTL engineers...
. Develop test logic RTL to achieve intended validation/characterization test. Drive new silicon product bring-up, validation...
architectural requirements into detailed hardware specifications. RTL Coding: Write clean, synthesizable, and high-performance RTL..., and develop functional coverage models. Closure: Run regressions, debug RTL/testbench mismatches, and achieve 100% code...
using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document... design methodologies, including RTL design, Lint, and CDC, to design digital or mixed signal products. DE running simulations...
and estimating power at every stage of the design from early RTL to final netlist and by driving ways to reduce power consumption... stages of design (RTL to gate level netlist) - Develop and maintain dashboards for power rollups - Work with designers...
. Collaborate with teams across the globe. Engineers interact with architects, RTL designers, performance engineers, and post... simulation fails. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers...
, RTL design, design verification, firmware, and software teams to ensure our next-generation AI/ML accelerators meet the... networks, ML HW architecture, and/or CI/CD - Familiarity with the validation lifecycle from RTL simulation (SystemVerilog/UVM...
from concept through silicon bring-up Define microarchitecture and drive RTL design and integration for high-performance and power... through silicon bring-up Deep expertise in RTL design, coding, and simulation using SystemVerilog Strong experience...