ASIC Design Engineer, Technical Leader

and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help... and waveform debug experience. Experience resolving setup and hold timing violations with RTL modification. Experience developing...

Lugar: San Jose, CA | 16/01/2025 18:01:34 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

ASIC Design Engineer, Senior Technical Leader

and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help... with RTL modification. Experience developing micro-architecture solutions and RTL implementation. Preferred Qualifications...

Lugar: San Jose, CA | 16/01/2025 18:01:38 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Sr. Physical Design Engineer

as the full-chip level from RTL to GDSII. You will collaborate with the Foundry Process Engineer, SoC Architect.... In-Depth Knowledge of design flow from RTL to GDSII. Good knowledge of EM-IR sign-off requirements. Experience in using EDA...

Lugar: Palo Alto, CA | 16/01/2025 18:01:24 PM | Salario: S/. $66.34 per hour | Empresa: Belcan

Computer Systems Engineer

. Familiarity with SoC design flow to include RTL, DFT, PD, Verification Hands-on development of low-level embedded system...

Lugar: Arlington, VA | 16/01/2025 03:01:37 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos

Senior System Engineer

. Familiarity with SoC design flow to include RTL, DFT, PD, Verification Hands-on development of low-level embedded system...

Lugar: Chula Vista, CA | 16/01/2025 03:01:20 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos

Senior System Engineer

. Familiarity with SoC design flow to include RTL, DFT, PD, Verification Hands-on development of low-level embedded system...

Lugar: El Cajon, CA | 16/01/2025 03:01:32 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos

Graphics FE Integration Engineer

. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural..., you will be responsible for: - RTL integration, partitioning, design analysis, qualification, packaging and delivery. - Run logic equivalence...

Lugar: Santa Clara, CA | 16/01/2025 03:01:04 AM | Salario: S/. No Especificado | Empresa: Apple

Senior System Engineer

. Familiarity with SoC design flow to include RTL, DFT, PD, Verification Hands-on development of low-level embedded system...

Lugar: Arlington, VA | 16/01/2025 03:01:19 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos

Computer Systems Engineer

. Familiarity with SoC design flow to include RTL, DFT, PD, Verification Hands-on development of low-level embedded system...

Lugar: San Diego, CA | 16/01/2025 03:01:15 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos