Wireless Sales Manager - Longview, TX
:** 18883 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
Lugar: Longview, TX | 30/12/2025 21:12:19 PM | Salario: S/. $45000 - 50000 per year | Empresa: Acosta
R&D IC Design Engineer
design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... experiences ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design...
Lugar: Irvine, CA | 30/12/2025 20:12:33 PM | Salario: S/. $91000 - 146000 per year | Empresa: Broadcom
R&D IC Design Engineer
, RTL/gate level simulations & silicon debugging scripting for various IC design tasks such as STA, equivalency checks... and problem solving skills as well as hands-on lab debugging experiences Good knowledge of RTL simulation and synthesis...
Lugar: Irvine, CA | 30/12/2025 19:12:35 PM | Salario: S/. No Especificado | Empresa: Broadcom
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design...
R&D IC Design Engineer
design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... experiences ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design...
Lugar: Irvine, CA | 30/12/2025 18:12:11 PM | Salario: S/. $91000 - 146000 per year | Empresa: Broadcom
Physical Design Engineer II (Silicon Engineering)
, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow...
District Manager - Wireless
, LLC **Req ID:** 18749 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
Lugar: Lubbock, TX | 30/12/2025 18:12:11 PM | Salario: S/. $75000 - 85000 per year | Empresa: Acosta
SOC/ASIC Physical Design Engineer II (Silicon Engineering)
, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow...
Senior Engineer - Design for Test (DFT)
test plans and engage closely with verification engineers to perform waveform reviews. Ensure RTL quality pre-DFT to ensure... the RTL is good for DFT insertion and coverage. Hold a primary role in enabling silicon by working directly with test...
Lugar: Hillsboro, OR | 30/12/2025 18:12:54 PM | Salario: S/. No Especificado | Empresa: Microsoft
Senior System Power Architect
, GPU, DSP, TPU) Knowledge of RTL code such as VHDL or Verilog and FPGA implementation flow (RTL, synthesis, P&R, timing...
Lugar: San Jose, CA | 29/12/2025 20:12:24 PM | Salario: S/. $175000 - 219000 per year | Empresa: Lattice Semiconductor