Principal ASIC Design Engineer (Silicon Engineering)

-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis... engineering, computer engineering, or computer science 10+ years of experience in RTL implementation and/or FPGA/ASIC development...

Lugar: USA | 23/12/2025 18:12:10 PM | Salario: S/. No Especificado | Empresa: SpaceX

Senior Pre-Silicon Verification Engineer

. Finds and implements corrective measures to resolve failing tests. Collaborates with CPU architects, RTL developers.../C++ System Verilog coding and debug Experience with RTL development Knowledge of system level boot flows and power...

Lugar: Austin, TX | 21/12/2025 03:12:21 AM | Salario: S/. No Especificado | Empresa: Intel

Senior Video Design Engineer

-architecture and RTL to meet performance, area, and power requirements Reviewing linting, synthesis, CLP, CDC, and DV coverage... and managing multiple tasks Principal duties: RTL implementation using Verilog/SystemVerilog Design optimization for power...

Lugar: San Diego, CA | 21/12/2025 02:12:07 AM | Salario: S/. $122500 - 183700 per year | Empresa: Qualcomm