SoC Digital Design Engineer, Multimedia Lab

(Power, Performance, Area) evaluation during the early design phase. - RTL Implementation: Write high-quality, well...-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation. - Front-End Quality Control: Perform Lint...

Lugar: San Jose, CA | 04/04/2026 02:04:38 AM | Salario: S/. No Especificado | Empresa: TikTok

Infinity Fabric Verification Engineer

. Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise... to RTL design, software development, formal verification, or other related domains. 7-12 years industry experience...

Lugar: Austin, TX | 04/04/2026 01:04:26 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Senior CPU Power Management Architect

. Collaborate with RTL designers, SoC architects, and firmware/OS teams to ensure power management algorithms are implemented...-power design, RTL development, and System Verilog. Proven ability to debug microarchitecture and simulation issues...

Lugar: Austin, TX | 04/04/2026 01:04:05 AM | Salario: S/. No Especificado | Empresa: Intel

Senior SoC Digital Design Engineer, Multimedia Lab

(Power, Performance, Area) evaluation during the early design phase. - RTL Implementation: Write high-quality, well...-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation. - Front-End Quality Control: Perform Lint...

Lugar: San Jose, CA | 04/04/2026 00:04:37 AM | Salario: S/. No Especificado | Empresa: TikTok

Control Room - Vice President / Senior Vice President

, and Restricted Trading List (RTL) programs. This role serves as a central point of escalation and oversight for potential conflicts... and oversee the firm's Restricted Trading List (RTL), including adding, monitoring, and removing securities based on MNPI...

Lugar: Salt Lake City, UT | 03/04/2026 23:04:23 PM | Salario: S/. $140000 - 190000 per year | Empresa: iCapital