Principal ASIC Design Engineer (Starshield)

. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully..., or computer science. 8+ years of experience in RTL implementation and/or FPGA/ASIC development. PREFERRED SKILLS...

Lugar: USA | 04/04/2026 17:04:20 PM | Salario: S/. No Especificado | Empresa: SpaceX

Senior FPGA Engineer

expectations Required skills FPGA design experience including thorough design documentation, completion and review of RTL... blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design Ability...

Lugar: Englewood, CO | 04/04/2026 17:04:53 PM | Salario: S/. $130000 - 185000 per year | Empresa: SEAKR Engineering

SoC Digital Design Engineer, Multimedia Lab

(Power, Performance, Area) evaluation during the early design phase. - RTL Implementation: Write high-quality, well...-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation. - Front-End Quality Control: Perform Lint...

Lugar: San Jose, CA | 04/04/2026 02:04:34 AM | Salario: S/. No Especificado | Empresa: TikTok