ASIC Engineer, Power

to model performance and power. Build power estimation flows at various levels of abstraction: C-model, RTL, Gate, Layout... between performance and power. Post-silicon bring-up, debug and identify issues on emulator and RTL. Understanding of ASIC design...

Lugar: Austin, TX - Sunnyvale, CA | 17/01/2025 23:01:25 PM | Salario: S/. No Especificado | Empresa: Meta

ASIC Chip Lead / Front End Design Engineer

, and performance targets. - Develop detailed specifications for the chip’s components. RTL Design and Synthesis: - Use Synopsys... Design Compiler to create RTL (Register Transfer Level) designs. - Optimize RTL code for area, power, and performance...

Lugar: Minneapolis, MN | 17/01/2025 22:01:06 PM | Salario: S/. No Especificado | Empresa: Chelsea Search Group

Senior Physical Design Engineer (remote)

Lynx a plus RTL Hand-over experience a plus for RTL to GDS Experience with top-level floorplanning, bump-maps, RDL IO Pad... experience with compression, scan, TDF, and MEMBIST a plus Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate...

Lugar: Phoenix, AZ | 17/01/2025 21:01:38 PM | Salario: S/. No Especificado | Empresa: Chelsea Search Group

Senior Physical Design Engineer (remote)

Lynx a plus RTL Hand-over experience a plus for RTL to GDS Experience with top-level floorplanning, bump-maps, RDL IO Pad... experience with compression, scan, TDF, and MEMBIST a plus Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate...

Lugar: Longmont, CO | 17/01/2025 21:01:00 PM | Salario: S/. No Especificado | Empresa: Chelsea Search Group

ASIC Engineer, Implementation

. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints... for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them...

Lugar: Austin, TX - Sunnyvale, CA | 17/01/2025 21:01:59 PM | Salario: S/. No Especificado | Empresa: Meta

Senior ASIC Design Verification Engineer

design blocks and SOCs Implementing complex digital designs using reusable RTL methods (Verilog, VHDL, SystemVerilog.../Computer Science or equivalent 10+ years of direct industry experience with ASIC and/or SoC design A strong background in RTL...

Lugar: Minneapolis, MN | 17/01/2025 20:01:30 PM | Salario: S/. No Especificado | Empresa: Chelsea Search Group