, RTL/gate level simulations & silicon debugging scripting for various IC design tasks such as STA, equivalency checks... and problem solving skills as well as hands-on lab debugging experiences Good knowledge of RTL simulation and synthesis...
design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design for test...
design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... experiences ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design...
:** 18883 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... experiences ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design...
, LLC **Req ID:** 18749 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
, LLC **Req ID:** 18884 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
efficient RTL to achieve design targets and specifications. - Analyze design, microarchitecture or architecture to make trade...-offs based on features, power, performance or area requirements. - Develop micro-architecture, implement SystemVerilog RTL...
, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow...
, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow...