Director of Business Development

, with teams in Ottawa, Waterloo, and San Jose focusing on FPGA design, embedded software, ASIC RTL design and verification...

Lugar: USA | 24/12/2025 18:12:11 PM | Salario: S/. No Especificado | Empresa: Fidus Systems

Senior ASIC Design Engineer

Design teams to ensure RTL quality supports timing closure, power targets, and manufacturability on advanced process nodes...

Lugar: San Jose, CA | 24/12/2025 18:12:18 PM | Salario: S/. No Especificado | Empresa: Persimmons

ASIC Design Verification Engineer - New College Grad 2026

related verification methodologies for the corresponding design (RTL). For this position, you should have real passion.... Strong coding skills in Python or other industry-standard scripting languages. Strong understanding of RTL design (Verilog...

Lugar: Austin, TX | 24/12/2025 01:12:53 AM | Salario: S/. $108000 - 184000 per year | Empresa: Nvidia

Design Engineer – AI SoC Development

ideal candidate for this role. Join us to shape the future of AI hardware. What You'll Do As an RTL Design Engineer..., you'll develop logic design, register transfer level (RTL) coding, and simulation for SoC designs, integrating IP blocks...

Lugar: Folsom, CA | 23/12/2025 19:12:16 PM | Salario: S/. No Especificado | Empresa: Intel

FE Design Verification Engineer (FE Infra)

verification, regression management, coverage analysis, RTL architecture, tool deployment, and interaction with industry-leading... closure You successfully deploy and maintain tools for RTL architecture, ensuring seamless integration with FE verification...

Lugar: Austin, TX | 23/12/2025 18:12:49 PM | Salario: S/. No Especificado | Empresa: Samsung

Director of Business Development

, with teams in Ottawa, Waterloo, and San Jose focusing on FPGA design, embedded software, ASIC RTL design and verification...

Lugar: USA | 23/12/2025 18:12:30 PM | Salario: S/. No Especificado | Empresa: Fidus Systems

Principal ASIC Design Engineer (Silicon Engineering)

-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis... engineering, computer engineering, or computer science 10+ years of experience in RTL implementation and/or FPGA/ASIC development...

Lugar: USA | 23/12/2025 18:12:53 PM | Salario: S/. No Especificado | Empresa: SpaceX

Sr. ASIC Design Engineer (Silicon Engineering)

, performance requirements and system limitations Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate... in RTL implementation PREFERRED SKILLS AND EXPERIENCE: Ability to solve complex problems including clock domain...

Lugar: USA | 23/12/2025 18:12:30 PM | Salario: S/. No Especificado | Empresa: SpaceX