SoC Verification Engineer – NoC / UVM

of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys... to regression management is a plus. Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC...

Lugar: San Jose, CA | 12/06/2026 19:06:20 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

CAD/EDA Tools Automation Engineer

Qualifications: 12+ months of experience in the following: Industry-standard EDA tools such as Cadence Virtuoso, Synopsys ICV...

Lugar: Hillsboro, OR | 12/06/2026 02:06:42 AM | Salario: S/. No Especificado | Empresa: Intel

Formal Verification - DV

methodology. Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal...

Lugar: San Jose, CA | 12/06/2026 00:06:25 AM | Salario: S/. No Especificado | Empresa: Etched