DFM RET Engineer
(e.g., Synopsys Sentaurus Lithography, Siemens EDA Calibre, ASML Brion) Familiarity with 28nm/22nm process constraints...
Lugar: Dallas, TX | 29/06/2026 18:06:54 PM | Salario: S/. No Especificado | Empresa: Texas Instruments
Digital IC Design Engineer
with synthesis and static timing analysis tools (Synopsys Design Compiler, Cadence Genus, or equivalent) Experience with low-power...
Lugar: Dallas, TX | 29/06/2026 18:06:47 PM | Salario: S/. No Especificado | Empresa: Texas Instruments
Principal Analog EDA Design Automation Engineer
with scripting, installing and managing EDA tools (Cadence, Mentor, Synopsys), and supporting IC design engineers by maintaining...
Lugar: Irvine, CA | 28/06/2026 22:06:43 PM | Salario: S/. $145000 - 190000 per year | Empresa: MaxLinear
Senior AI Solutions Architect - Semiconductors
., Cadence, Synopsys, Siemens EDA) and/or computational lithography, TCAD, or inspection/metrology systems. Experience...
Lugar: Santa Clara, CA | 28/06/2026 01:06:57 AM | Salario: S/. No Especificado | Empresa: Nvidia
Principal Analog EDA Design Automation Engineer
with scripting, installing and managing EDA tools (Cadence, Mentor, Synopsys), and supporting IC design engineers by maintaining...
Lugar: Irvine, CA | 27/06/2026 19:06:35 PM | Salario: S/. $145000 - 190000 per year | Empresa: MaxLinear
BE CAD Physical Impl and AI Engineer
and deploy next-generation EDA capabilities across both Synopsys and Cadence tool ecosystems. Collaborate with EDA vendors..., and power optimization. Strong hands-on experience with Synopsys Fusion Compiler and/or Cadence Innovus. Proven experience...
Lugar: Austin, TX | 27/06/2026 17:06:41 PM | Salario: S/. No Especificado | Empresa: Ericsson
DFT Engineer
of digital logic fundamentals. Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite. Proficiency...
Principal AI Forward Deployment Engineer
. Nice-to-Have / Bonus Prior experience as a Cadence / Synopsys / Siemens EDA customer power user, AE, or methodology...
Lugar: USA | 26/06/2026 01:06:29 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
SOC IP Methodology Engineer - Custom SOC
vendors such as Cadence, Synopsys, Mentor (CDC, LP Checks, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler...
Lugar: Santa Clara, CA | 26/06/2026 00:06:56 AM | Salario: S/. No Especificado | Empresa: Nvidia
Verification Engineer Senior
techniques relevant to ASIC/FPGA domain. Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent...
Lugar: Austin, TX | 25/06/2026 20:06:23 PM | Salario: S/. No Especificado | Empresa: Intel