Sr. RTL Design Engineer
analysis, and power analysis. Experience with Synopsys VCS, Verdi, or comparable simulation and debug tools. Experience...
Lugar: Palo Alto, CA | 16/09/2026 02:09:27 AM | Salario: S/. No Especificado | Empresa: Rivian
Digital Design Engineer
physical design and timing tools from vendors such as Cadence, Synopsys, or Siemens EDA. Strong scripting and automation...
Lugar: Louisville, CO | 15/09/2026 22:09:10 PM | Salario: S/. No Especificado | Empresa: Actalent
Senior Software Engineer, Design Infrastructure
with digital design methodologies and EDA tool ecosystems, including Synopsys, Cadence, or Siemens EDA, is a plus. Exposure...
Lugar: Colorado | 15/09/2026 22:09:38 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices
Design Engineer II
/MIPI exposure MSEE/CS Synopsys Core Consultant experience (IP configuration/generation and coreAssembler-based subsystem...
Lugar: Burlingame, CA | 15/09/2026 21:09:33 PM | Salario: S/. No Especificado | Empresa: US Tech Solutions
ASIC Physical Design
Synopsys tools for Timing Analysis job requirements below: Good understanding of Cadence tools (Innovous, Quantus, Voltus...
Lugar: San Jose, CA | 15/09/2026 20:09:21 PM | Salario: S/. No Especificado | Empresa: vaaridatech
Sr. Staff Physical Design Engineer, EMIR Analysis & Signoff
requirements. Proficiency in industry-standard PI/Signoff tools: Ansys RedHawk-SC, Cadence Voltus, or Synopsys PrimePower/Rail...
Lugar: Palo Alto, CA | 15/09/2026 17:09:20 PM | Salario: S/. No Especificado | Empresa: Rivian
Principal FPGA Emulation Engineer
-throughput techniques such as folding/unfolding. Experience with commercial FPGA prototyping platforms such as Synopsys HAPS...
Lugar: Austin, TX | 15/09/2026 17:09:40 PM | Salario: S/. No Especificado | Empresa: Renesas Electronics
Mid-level Physical Design Engineer CPU
with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis... techniques RTL to GDS methodologies and formal equivalence Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence...
Lugar: Hillsboro, OR | 13/09/2026 18:09:39 PM | Salario: S/. No Especificado | Empresa: Intel
Ph.D. Intern - AI/ML & Design Automation
(Cadence, Synopsys, or equivalent) is a strong plus Track 2 — Additional Requirements Design and implement agentic GenAI...
Lugar: Santa Clara, CA | 12/09/2026 01:09:20 AM | Salario: S/. $37 - 73 per hour | Empresa: Marvell
SoC Physical Design Senior Manager, HBM
, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent). Solid understanding of STA fundamentals, clocking, constraints (SDC...
Lugar: Folsom, CA | 11/09/2026 23:09:21 PM | Salario: S/. No Especificado | Empresa: Micron