RTL Design Engineer

utilizing RTL optimization strategies. Conduct formal verification of design with Synopsys Formality / Cadence Conformal...

Lugar: Chandler, AZ | 21/02/2026 00:02:43 AM | Salario: S/. No Especificado | Empresa: Broadcom

Memory Chip Design Engineer

, or Synopsys IC Validator Capability to work closely with circuit designers to iterate on schematics and with process engineers...

Lugar: San Jose, CA | 18/02/2026 20:02:42 PM | Salario: S/. $145800 - 194400 per year | Empresa: Western Digital

Staff DFT Engineer

Experience with EDA DFT tools (Siemens EDA Tessent, Cadence Modus, or Synopsys TestMAX) Demonstrable programming skills with TCL...

Lugar: Burlington, VT | 18/02/2026 03:02:25 AM | Salario: S/. $115200 - 170390 per year | Empresa: Marvell

ASIC/FPGA Design Engineer (SMES)

Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework.... Proficient with CDC, RDC. Formal EDA. Proficient in VHDL. Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado...

Lugar: Camden, NJ | 17/02/2026 19:02:55 PM | Salario: S/. $111515 - 151500 per year | Empresa: L3Harris Technologies