Formal Verification - DV

methodology. Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal...

Lugar: San Jose, CA | 11/06/2026 17:06:35 PM | Salario: S/. No Especificado | Empresa: Etched

Senior Analog Design Engineer

, and verification using industry-standard tools (Cadence, Synopsys, etc.) using approaches that enable automation and take advantage...

Lugar: Chandler, AZ | 11/06/2026 02:06:53 AM | Salario: S/. No Especificado | Empresa: Intel

Sr. Staff Physical Design Timing Engineer (STA)

and timing constraints development, timing closure with Cadence or Synopsys tools Experience in driving timing closure... in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools We offer competitive...

Lugar: Boston, MA | 10/06/2026 20:06:47 PM | Salario: S/. No Especificado | Empresa: Lightmatter

RTL/Logic Design Engineer

-standard CAD tools from Synopsys, Cadence, and Mentor Graphics, with strong skills in simulation, synthesis, and timing... development flows Strong RTL analysis skills including Verilog, Timing Analysis Working experience on CAD tools from Synopsys...

Lugar: Santa Clara, CA | 10/06/2026 18:06:16 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

SoC Design Engineer

EDA tools such as Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, and Integrator. Conduct chip bring-up, silicon...

Lugar: Santa Clara, CA | 10/06/2026 02:06:29 AM | Salario: S/. $156853 - 160000 per year | Empresa: OmniVision

Senior Electrical Systems Analysis (CAE) Engineer - 12V/48V

and proficiency in simulation tools such as Synopsys Saber. The senior analysis engineer is also required to have experience... in Synopsys Saber simulator, MAST modeling language, and electrical data analysis tools including MATLAB, Simulink, and Simscape...

Lugar: Warren, MI | 10/06/2026 00:06:18 AM | Salario: S/. No Especificado | Empresa: General Motors

Principal Physical Design Engineer

, and implementation solutions for advanced ASIC designs. The ideal candidate will have deep experience with Cadence Innovus, Synopsys... in: Cadence Innovus place and route, and/or Synopsys Fusion Compiler Physical design fundamentals (floorplan, placement, CTS...

Lugar: Sunnyvale, CA | 09/06/2026 20:06:03 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise